This invention relates to “hybrid” programmable logic devices having mask-programmable portions as well as field-programmable portions. More particularly, this invention relates to mask-programmable logic devices in which at least some of the input/output and/or clock circuitry is programmable by the user even after mask programming has occurred.
Programmable logic devices are well known. Early programmable logic devices were one-time configurable. For example, configuration may have been achieved by “blowing”—i.e., opening—fusible links. Alternatively, the configuration may have been stored in a programmable read-only memory. These devices generally provided the user with the ability to configure the devices for “sum-of-products” (or “P-TERM”) logic operations. Later, such programmable logic devices incorporating erasable programmable read-only memory (EPROM) for configuration became available, allowing the devices to be reconfigured.
Still later, programmable logic devices incorporating static random access memory (SRAM) elements for configuration became available. These devices, which also can be reconfigured, store their configuration in a nonvolatile memory such as an EPROM, from which the configuration is loaded into the SRAM elements when the device is powered up. These devices generally provide the user with the ability to configure the devices for look-up-table-type logic operations.
In all of the foregoing programmable logic devices, both the logic functions of particular logic elements in the device, and the interconnect for routing of signals between the logic elements, were programmable. More recently, mask-programmable logic devices (“MPLDs”) have been provided. With MPLDs, instead of selling all users the same device, the manufacturer manufactures a partial device with a standardized arrangement of logic elements whose functions are not programmable by the user, and which lacks certain routing or interconnect resources.
The user provides the manufacturer of the MPLD with the specifications of a desired device, which may be the configuration file for programming a comparable conventional programmable logic device. The manufacturer uses that information to add metallization layers to the partial device described above. Those additional layers program the logic elements by making certain connections within those logic elements, and also add interconnect routing between the logic elements.
While conventional programmable logic devices allow a user to easily design a device to perform a desired function, a conventional programmable logic device invariably includes resources that may not be used for a particular design. Moreover, in order to accommodate general purpose routing and interconnect resources, and the switching resources that allow signals from any logic element to reach any desired routing and interconnect resource, conventional programmable logic devices grow ever larger as more functionality is built into them, increasing the size and power consumption of such devices. The routing of signals through the various switching elements as they travel from one routing and interconnect resource to another also slows down signals.
The advent of MPLDs has allowed users to prove a design in a conventional programmable logic device, but to commit the production version to an MPLD which, for the same functionality, can be significantly smaller and use significantly less power, because the only interconnect and routing resources are those actually needed for the particular design. In addition, those resources are simple metallizations, so there are no general purpose switching elements consuming space or power, or slowing down signals.
Although MPLDs have the foregoing advantages, it may happen from time to time that there is a change in the environment in which a programmed MPLD (i.e., a mask-programmed logic device) is used. A mask-programmed logic device almost invariably is used in a system including other components. It may happen, after the design of a mask-programmed logic device for use in such a system, that parameters of the system change in such a way that, while the logical operation of the mask-programmed logic device need not change, the input/output (“I/O”) characteristics do change—e.g., because some other component of the system had to be changed. With known MPLDs, that would necessitate a redesign of the programming metallization layers to accommodate the new I/O characteristics, even though the logic has not changed.
Similarly, environmental changes may affect clock speeds in a way that requires adjustment of clock characteristics of an MPLD. Although it is known to allow the logic core of an MPLD to adjust clock characteristics of the device, those adjustments can be made only when the logic has been predesigned to make them. Therefore, unless the environmental condition requiring clock adjustments is foreseen, and the logic is designed to test for it so that it can be detected and acted upon, known MPLDs cannot accommodate environmental changes that affect clock characteristics.
Accordingly, it would be advantageous to be able to provide a mask-programmable logic device that provides the size and speed advantages of previously known mask-programmable logic devices, but also can more easily accommodate necessary changes resulting from environmental conditions.